Semiconductor memory device and layout structure of sub-word line control signal generator

ABSTRACT

A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation Application of U.S. patentapplication Ser. No. 12/177,716, filed on Jul. 22, 2008, in the U.S.Patent and Trademark Office, which claims priority under 35 U.S.C. §119(a) from Korean Patent Application 10-2007-0077956, filed on Aug. 3,2007, in the Korean Intellectual Property Office, the disclosure ofwhich is incorporated herein in its entirety by reference.

BACKGROUND

1. Technical Field

The present invention relates to semiconductor memory devices, and moreparticularly, to a semiconductor memory device and a layout structure ofa sub-word line control signal generator, capable of reducing powerconsumption and noise and improving an enable speed of the sub-word lineby providing a relatively differential layout of the sub-word linecontrol signal and a sub-word line control signal supply line.

2. Description

In general, as a DRAM (Dynamic Random Access Memory) becomes relativelyhighly integrated and larger in capacity, a time required to transfer asignal increases as compared with a delay time of a memory cell arrayitself due to a resistance problem of wire. As a result, a length of thewire needs to be appropriately divided to optimize a delay time. Forexample, a word line to select a row in the memory cell array isappropriately divided to optimize the delay time.

A word line is coupled to a gate terminal of an access transistorconstituting a memory cell, and is generally formed of polysilicon.Specific resistance of polysilicon may be high. Moreover a capacitancemay be high since the word line passes an upper part of gate oxide of acell transistor. In other words, when a resistance of the word linebecomes great, an RC delay increases and a decoder output terminaldriving the word line should be large. Thus, an area size increases andmuch power is consumed in charging the entire word line to a highvoltage, and then discharging it. Therefore, the length of the word lineneeds to be optimized to reduce resistance.

One approach to solve this problem has been to use a hierarchicaldivided word line structure to drive a sub-word line. The structure caninclude dividing a word line into sub-word lines of proper length andcombining a main word line of a row decoder and sub-word lines of asub-word line driver.

In the hierarchical word line structure, a word line is divided intoproper lengths and is provided as sub-word lines SWL, and the sub-wordlines SWL are driven by a row decoder and a sub-word line driver SWD.The row decoder may be classified as a main word line driver MWD and asub-word line control signal generator (hereinafter, referred to as ‘PXIgenerator’).

The SWD is controlled by a main word line signal NWE output from the MWDand a sub-word line control signal PXI output from the PXI generator.

FIG. 1 illustrates a layout related to a word line selection in asemiconductor memory device according to a conventional art. As shown inFIG. 1, a plurality of memory blocks MBi, MBj and MBk are disposed in ahorizontal second direction. Each of the memory blocks MBi, MBj and MBkcomprise a plurality of sub-memory blocks SMB arrayed in a verticalfirst direction.

In a row decoder area, PXI generators PG13 and PG02 are configured togenerate a sub-word line control signal PXI<0-3>. An MWD is configuredadjacent to the PXI generators PG13 and PG02. Further, a sub-word linecontrol driver (PXI driver) PD for amplifying sub-word line controlsignal PXI<0-3> generated in the PXI generators PG13 and PG02, andsupplying the signal to the sub-word line driver SWD, is disposed on aconjunction area of a memory core region. The sub-word line controldrivers PD use a high voltage of VPP level as a power source voltage,and drive output signals as a high voltage (VPP) level.

The SWD is disposed in an area between two sub-memory cell blocks SMB ina vertical direction. The SWD drives a sub-word line (not shown) inresponse to a main word line signal NWE generated in the MWD and outputsignals PXID of the sub-word line control driver PD.

The sub-word line control signal PXI and the output signals PXID of thesub-word line control driver PD have the same voltage level, and theoutput signals PXID of the sub-word line control driver PD are signalsamplified from the sub-word line control signal PXI, thus all of themare commonly called herein a sub-word line control signal PXI.

Operation to drive a sub-word line is described as follows. A rowaddress RA to select a desired sub-word line is applied. For example,when the row address RA is 14 bits, a portion RA13-2 of row address isinput to the MWD, i.e., reference number 10, and the rest of the rowaddress RA1-0 is input to the PXI generators PG13 and PG02. The mainword line driver 10 generates a block selection signal BS into the PXIgenerators PG13 and PG02, to activate or select a PXI generator, i.e.,reference numbers 12 and 14, corresponding to a specific memory block,i.e., MBj.

The PXI generators 12 and 14 generate the sub-word line control signalPXI into any one of plural, i.e., four, sub-word line control signalsupply lines, in response to the row address RA1-0. For example, the PXIgenerator 12 generates a first sub-word line control signal PXI1. Thefirst sub-word line control signal PXI1 is amplified by the sub-wordline control driver 30 and supplied to a sub-word line driver 40. Thesub-word line driver 40 enables one sub-word line in response to thefirst sub-word line control signal PXI1 and main word line signal NEWsupplied through a main word line MWL from the main word line driver 10.The main word line signal NWE may have a row enable state. The enablestate of the sub-word line may be accomplished by performing a switchingoperation to supply the first sub-word line control signal PXI1 to aselected sub-word line.

In a conventional semiconductor memory device having the structuredescribed above, respective ones of sub-word line control drivers PD arealternately disposed every two sub-array memory blocks SMB. Further,output lines of the sub-word line control drivers PD, that is, supplylines of sub-word line control signals PXI<1,3> and PXI<0,2>, aredisposed as a T-shape in horizontal and vertical directions. Thus, theline length of sub-word line control signals PXI<1,3> and PXI<0,2> isrelatively long and a load thereof is relatively large. Thus, VPP powerconsumption through the sub-word line control drivers PD may be great,and a drive speed for the sub-word line may be relatively slow.

Furthermore, it is the structure that one sub-word line control signalPXI is supplied even to a non-selected memory block, i.e., MBi, thus aVPP power consumption is great. And, as the sub-word line control driverPD is disposed at a conjunction area of a memory core region, aplurality of VPP power lines to supply a VPP power source to thesub-word line control drivers PD must be used. The VPP power lines maybe disposed overlapping in an upper part of memory block or disposed ina core region. The VPP power lines acts as a noise source in asemiconductor memory device, thus causing a noise disturbance.

Accordingly, some embodiments of the invention provide a semiconductormemory device and a layout structure of a PXI generator. Powerconsumption and noise can be reduced. In addition, an enable speed of asub-word line can be improved. Furthermore, a VPP voltage consumptioncan decrease, while maintaining high integration.

According to an embodiment of the invention, a layout structure ofsub-word line control signal (PXI) generator may be configured to supplya sub-word line control signal of a predefined voltage level to asub-word line driver to enable a sub-word line of a memory cell arraymay be characterized in that at least two sub-word line control signalgenerators are disposed, respectively, at edge areas of an area of thememory cell array, and configured to directly supply the sub-word linecontrol signal to one selected sub-word line driver.

The sub-word line control signal may be directly supplied from the PXIgenerator to the sub-word line driver without a specific driver,amplifier, or repeater. The memory cell array may comprise a pluralityof memory blocks, each memory block having an area including a pluralityof sub-memory blocks arrayed in a first direction, the plurality ofmemory blocks being arrayed in a second direction intersected to thefirst direction, and wherein the sub-word line driver may be disposed atcore regions between the sub-memory blocks.

A supply line of the sub-word line control signal may be disposedoverlapping on one memory block area in the first direction, the firstdirection being a length-wise direction, to supply the sub-word linecontrol signal to at least one sub-word line driver adapted within theone memory block area. The predefined voltage level may be a VPP voltagelevel higher than an array voltage supplied to the memory cell array.

The PXI generator may generate the sub-word line control signal inresponse to a given address signal. The sub-word line control signalsupply line may be disposed so as to simultaneously supply the sub-wordline control signal from the at least two sub-word line control signalgenerators to sub-word line drivers included in at least two memoryblocks.

According to another embodiment of the invention, a semiconductor memorydevice comprises a plurality of memory blocks, each memory block havingan area including a plurality of sub-memory blocks arrayed in a firstdirection, the plurality of memory blocks being arrayed in a seconddirection intersected to the first direction; a plurality of sub-wordline control signal generators, of which at least two correspond to onesub-word line of a sub-memory block, and are disposed, respectively, atedge areas of a memory block, the plurality of sub-word line controlsignal generators configured to generate a sub-word line control signal;a plurality of sub-word line drivers configured to supply a signalhaving the same level as the sub-word line control signal to the onesub-word line, the plurality of sub-word line drivers being disposed ina core region between the sub-memory blocks; and control signal supplylines for directly supplying the sub-word line control signal to theplurality of sub-word line drivers without using a repeater, thesub-word line control signal being generated using the sub-word linecontrol signal generators, the sub-word line control signal having apredefined voltage level.

Each of the PXI generators may have a structure to generate a sub-wordline control signal of a predefined voltage level in response to a givenaddress signal and to supply the sub-word line control signal to atleast one sub-word line driver of one memory block selected withoutbeing supplied to other memory blocks.

Supply lines corresponding to one sub-word line control signal among thecontrol signal supply lines may comprise a first supply line disposed ina first direction as a length direction and a second supply linedisposed in a second direction as a width direction. The first supplyline may be coupled between the at least two sub-word line controlsignal generators that are disposed at both edge areas of the memoryblock in the first direction, and the second supply line may be disposedto couple at least one corresponding sub-word line driver with the firstsupply line. The first supply line may be disposed overlapping on thememory block area.

The PXI generator may generate the sub-word line control signal inresponse to the given address and a block selection signal to select amemory block. The sub-word line control signal may be supplied tosub-array blocks adapted within at least two adjacent memory blocks.

According to another embodiment of the invention, a layout structure ofPXI generator may be configured to supply a sub-word line control signalto a sub-word line driver to enable a sub-word line of a memory cellarray may be characterized in that the PXI generator corresponds to onesub-word line driver, the sub-word line control signal generator beingdivided into a main generator and a sub-generator for simultaneouslysupplying the sub-word line control signal to one supply line, the maingenerator and the sub-generator being disposed, respectively, at edgeareas of the memory cell array.

The main generator may be disposed at a row decoder area about an edgearea of the memory cell array, and the sub-generator may be disposed atan area opposite to a layout area of the main generator. The memory cellarray may comprise a plurality of memory blocks arrayed in a seconddirection intersected to a first direction, each memory block includinga plurality of sub-memory blocks arrayed in the first direction, thesub-word line driver being disposed in core regions within an area ofeach memory block.

The supply line may be disposed overlapping the memory block in thefirst direction, the first direction being a length-wise direction.

According to some embodiment of the invention, power consumption can bereduced including that of VPP voltage, and the number of VPP power linescan be reduced, thereby decreasing noise. In addition, a memory coreregion can be utilized, thereby obtaining a high integration.Furthermore, a word line can be enabled without a speed decrease evenwithout adapting a sub-word line control driver.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given herein below, and the accompanying drawings,which are given by way of illustration only, and thus are not limitativeof the present invention, wherein:

FIG. 1 illustrates a layout related to a word line selection in asemiconductor memory device according to a conventional art;

FIG. 2 illustrates a layout structure of semiconductor memory deviceaccording to an embodiment of the invention;

FIG. 3 illustrates a partially enlarged view of FIG. 2;

FIG. 4 is a circuit diagram illustrating an embodiment of the sub-wordline driver shown in FIG. 3; and

FIG. 5 illustrates a layout structure of a semiconductor memory deviceaccording to another embodiment of the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention now will be described more fullyhereinafter with reference to FIGS. 2 to 5, in which example embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein. Rather these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.Exemplary embodiments of the present invention are more fully describedbelow with reference to FIGS. 2 to 5. This invention may, however, beembodied in many different forms and should not be construed as beinglimited to the exemplary embodiments set forth herein; rather, theseexemplary embodiments are provided so that this disclosure is thoroughand complete, and conveys the concept of the invention to those skilledin the art.

FIG. 2 illustrates a layout structure of semiconductor memory deviceaccording to an embodiment of the invention. FIG. 3 illustrates apartially enlarged view of FIG. 2. FIG. 3 illustrates an enlargedportion of area of first memory block MB1 shown in FIG. 2.

Referring to FIGS. 2 and 3, a semiconductor memory device according toan embodiment of the invention comprises a plurality of memory blocksMB1-MBn, a plurality of PXI generators PG13 and PG02, a plurality ofsub-word line drivers SWD, and control signal supply lines L1 and L2.

The plurality of memory blocks MB1-MBn each comprises a plurality ofsub-memory blocks SMB arrayed in a first direction, and are arrayed in asecond direction intersected to the first direction. That is, in thestructure, the plurality of sub-memory blocks SMB are regularly arrayed,sub-memory blocks SMB arrayed in the first direction are defined as onememory block, i.e., MB1, and the memory blocks may have a structure ofbeing disposed in plural numbers in the second direction. The pluralityof memory blocks MB1-MBn may constitute a memory cell array of thesemiconductor memory device. That is, the plurality of memory blocksMB1-MBn may be disposed in a memory cell array area.

The PXI generators PG13 and PG02 are adapted in plural numbers so thatat least two respective generators correspond to one sub-word line SWLof the sub-memory block SMB. The at least two PXI generatorscorresponding to the one sub-word line may be disposed, respectively, atboth edge areas of the memory blocks MB1-MBn arranged in a firstdirection.

The PXI generator PG13 may generate a first sub-word line control signalPXI1 and a third sub-word line control signal PXI3. The PXI generatorPG02 may generate a zeroth sub-word line control signal PXIO and asecond sub-word line control signal PXI2. The sub-word line controlsignal PXI may have four signals. Two PXI generators, i.e., two PG13 ortwo PG02, may be disposed to generate one sub-word line control signalPXI.

For example, as shown in FIG. 3, at least two PXI generators 112 a and112 b are adapted to supply a sub-word line control signal PXI1 to onesub-word line driver 140. The PXI generators 112 a and 112 b aredisposed at both edge areas of the memory block MB 1. The PXI generators112 a and 112 b operate in response to a given row address RAI.

The plurality of sub-word line drivers SWD supply a signal having thesame level as the sub-word line control signal PXI in response to thesub-word line control signal PXI to a corresponding sub-word line. Thesub-word line drivers SWD may be disposed in a core region betweensub-memory blocks SMB adjacent in a first direction. For example, onesub-word line driver 140 may be disposed on a core region betweensub-array memory blocks 120 and 122 adjacent mutually in the firstdirection. Operation and structure of the sub-word line driver SWD aredescribed below with reference to FIG. 4.

Control signal supply lines LI and L2 may supply the sub-word linecontrol signal that is generated in the PXI generators PG13 and PG02 andthat has a predefined voltage level, i.e., VPP voltage level, directlyto the sub-word line driver SWD without a specific driver, amplifier, orrepeater. The control signal supply lines LI and L2 are classified as afirst supply line L1 and a second supply line L2. The first supply lineLI is disposed in the first direction as a length direction to connectrespective PXI generators PG13 or PG02 adapted in both edge areas ofmemory block MBi. The second supply line L2 is disposed in a seconddirection to supply a signal of the first supply line L1 to the sub-wordline driver SWD.

As shown in FIG. 3, the first supply line L1 is disposed to connectbetween at least two PXI generators P112 a and 112 b adapted at bothedge areas of the memory block in the first direction. The second supplyline L2 is disposed to connect at least one or more correspondingsub-word line drivers 140 with the first supply line L1. The secondsupply line may be coupled to sub-word line driver 140 configured aboutone memory block MB 1. In other words, it may be coupled to onlysub-word line driver 140 of a selected memory block MB1. In this case,the first supply line L1 may have a structure of being not disposed in acore region, but rather disposed overlapping on the memory block area.

According to an embodiment of the invention, and unlike the conventionalart, a specific sub-word line control driver, amplifier, or repeater,etc., to supply sub-word line control signal PXI to sub-word line driverSWD, is not used. As a result, a high integration can be obtained bysaving a layout space that would otherwise be needed for the sub-wordline control driver, amplifier, or repeater. Furthermore, a noisereduction can be obtained by omitting a layout of a power line of apredefined voltage level to drive the specific sub-word line controldriver, amplifier, or repeater, thereby saving the layout space thatwould otherwise be needed for the power line.

Referring to an enlarged view of FIG. 3, representing a core region ofsub-memory blocks 120 and 122 within first memory block MB 1, a layoutarea may include PXI generators 112 a and 112 b disposed at edge areasof first memory block MB1, and control signal supply lines Li and L2referred to in FIG. 2. The layout structure is described in more detailas follows. FIG. 3 illustrates only one sub-word line driver 140 betweenspecific memory blocks 120 and 122 among a plurality of sub-word linedrivers SWD, and only a sub-word line control signal PXI1 correspondingto the sub-word line driver 140 and corresponding control signal supplylines L1 and L2. The layout structure of FIG. 3 may be equally appliedto other memory blocks MB2-MBn.

As shown in FIG. 3, PXI generators 112 a and 112 b may be disposed atboth edge areas of first memory block MB 1. The PXI generator 112 bdisposed at an upper edge area of the memory block MB 1 is called hereina sub-generator, and the PXI generator 112 a disposed at a row decoderarea 150 as a lower edge area of the memory block MB 1 is called hereina main generator.

The main generator 112 a and the sub-generator 112 b have substantiallythe same structure and operation, and generate sub-word line controlsignal PXI1 in response to a given row address RA1 and block selectionsignal BS. For such operation, a supply line may be disposed to supplythe block selection signal BS to the sub-generator 112 b, and a supplyline may be disposed to supply a given row address RA1.

At the row decoder area 150, at the lower edge area of the memory blockMB1, the main generator 112 a may be disposed adjacent a main word linedriver 110. The main word line driver 110 may provide main word linesignal NWE to the sub-word line driver 140. The main word line signalNWE may be supplied through main word line MWL. The main word linedriver 110 provides the block selection signal BS to the main generator112 a and the sub-generator 112 b.

The first supply line L I may be disposed with the first direction as alength direction to connect between the main generator 112 a and thesub-generator 112 b. The first supply line L1 is disposed at a coreregion according to a conventional art, but herein is disposedoverlapping on an upper area of the memory block MB1 according to anembodiment of the invention. Accordingly, a utilized extent of the coreregion can increase.

The second supply line L2 may be disposed in the second direction as awidth direction to supply sub-word line control signal PXI1 of the firstsupply line L1 to the sub-word line driver 140. Unlike the conventionalart, the second supply line L2 is disposed to supply the control signalto only the sub-word line driver 140 adapted within one memory block MB1. Unlike the conventional ‘T’-shaped structure, the second supply lineL2 has the layout structure of being connected to only the sub-word linedriver 140 of one memory block MB1. That is, the structure is to supplythe sub-word line control signal PXI1 generated in the sub-generator 112b and the main generator 112 a to only the sub-word line driver 140 ofone memory block MB1, but not to supply it to sub-word line driver SWDof another memory block. Consequently, a length of second supply line isreduced, thereby lessening a load and a power consumption, such as a VPPcharge consumption, etc.

Sub-word line control signal PXID1 provided through the second supplyline L2 is called ‘PXID 1’ herein to discriminate from the sub-word linecontrol signal PXI1 supplied through the first supply line L 1.Additionally, a floating prevention signal PXIB 1 to prevent a sub-wordline coupled to the sub-word line driver 140 from floating may besupplied through a driver DI, inverting the sub-word line control signalPXI1.

FIG. 4 is a circuit diagram illustrating an embodiment of the sub-wordline driver 140 shown in FIG. 3. As shown in FIG. 4, the sub-word linedriver 140 comprises a PMOS transistor P142 and NMOS transistors N144and N146. The sub-word line driver 140 drives sub-word line SWL inresponse to the main word line signal NWE input through main word lineMWL, sub-word line control signal PXID1, and the floating preventionsignal PXIB1, as a complementation sub-word line control signal. Thecircuit of FIG. 4 is an example of a sub-word line driver SWD andpersons having skill in the art will recognize that it may be configuredin various other ways.

Referring to FIGS. 3 and 4, an operation to drive a sub-word line isdescribed as follows. First, a row address RA is applied to select arequired sub-word line. The row address RA may be 14 bits. A portion RA2of the row address may be applied to the main word line driver MWD,i.e., 110, and the rest of the row address RA1 may be applied to themain generator 112 a and the sub-generator 112 b. The main word linedriver 110 generates and transmits block selection signal BS to the maingenerator 112 a and the sub-generator 112 b, thereby activating orselecting the main generator 112 a and sub-generator 112 b correspondingto the first memory block MB 1. The block selection signal BS is assumedherein as a signal to select the first memory block MB1.

The main generator 112 a and the sub-generator 112 b may simultaneouslytransmit signals into the first supply line LI among a plurality, i.e.,four, of sub-word line control signals PXIO-PXI3, in response to the rowaddress RA1 and the block selection signal BS. The first sub-word linecontrol signal PXI1 is supplied to the sub-word line driver 140 throughthe second supply line L2 connected to the first supply line L1 withoutpassing through a specific driver, amplifier, or repeater.

The sub-word line driver 140 may enable one sub-word line SWL inresponse to the sub-word line control signal PXIDI and the main wordline signal NWE supplied through the main word line MWL from the mainword line driver 110.

FIG. 5 illustrates a layout structure of a semiconductor memory deviceaccording to another embodiment of the invention. As shown in FIG. 5, asemiconductor memory device according to an embodiment of the inventionhas a structure different from the layout structure described referringto FIGS. 2 and 3.

Unlike the description referred to in FIGS. 2 and 3, in FIG. 5 one maingenerator, i.e., 212 a, and one sub-generator, i.e., 212 b, have alayout structure to supply a signal to the sub-word line driver adaptedwithin at least two memory blocks. That is, the structure is providedherein so that one sub-word line control signal PXI is suppliedsimultaneously to at least two memory blocks, i.e., MBi and MBj. Insupplying the sub-word line control signal PXI, a specific repeater,amplifier, or driver is not used.

In FIGS. 2 and 3, respective one main generator and sub-generator areadapted for one memory block. On the other hand, FIG. 5 has the layoutstructure that two memory blocks, i.e., MBi and MBj share each one maingenerator 212 a and sub-generator 212 b. Supply lines to supply sub-wordline control signal PXI1 and PXI3 may be disposed in a core regionbetween the memory blocks MBi and MBj with the first direction as alength direction. Lines to supply block selection signal BS may bedisposed near the supply lines. Further, a layout of main word linedriver 210 may be the same as FIGS. 2 and 3, and a layout structure ofmemory blocks MBi, MBj and MBk and sub-memory blocks SMB may be the sameas FIG. 2.

As described above, according to some embodiments of the invention,there is provided a structure to simultaneously generate a sub-word linecontrol signal corresponding to one sub-word line or one sub-word linedriver by using a main generator and a sub-generator that are disposedat both edge areas of a memory block. In addition, the layout structureis provided to directly supply a sub-word line control signal generatedin the main generator and sub-generator to a sub-word line driverwithout a specific repeater or driver.

According to some embodiments of the invention, power consumption can bereduced including the VPP voltage, and the number of VPP power lines canbe reduced, thereby decreasing noise. In addition, a memory core regioncan be utilized, thereby obtaining a high integration. Furthermore, aword line can be enabled without a decrease of speed, and without asub-word line control driver.

It will be apparent to those skilled in the art that modifications andvariations can be made in the present invention without deviating fromthe spirit or scope of the invention. Thus, it is intended that thepresent invention cover any such modifications and variations of thisinvention provided they come within the scope of the appended claims andtheir equivalents. Accordingly, these and other changes andmodifications are seen to be within the true spirit and scope of theinvention as defined by the appended claims.

In the drawings and specification, there have been disclosed typicalembodiments of the invention and, although specific terms are employed,they are used in a generic and descriptive sense only and not forpurposes of limitation, the scope of the invention being set forth inthe following claims.

1. A layout structure of a sub-word line control signal generatorconfigured to supply a sub-word line control signal to a sub-word linedriver to enable a sub-word line of a memory cell array, the structurecomprising: at least two sub-word line control signal generatorsdisposed, respectively, at edge areas of an area of the memory cellarray, and configured to directly supply the sub-word line controlsignal to one selected sub-word line driver, the at least two sub-wordline control signal generators supplying an equal sub-word line controlsignal to the selected sub-word line driver.
 2. The structure of claim1, wherein the sub-word line control signal is of a predefined voltagelevel and directly supplied from the at least two sub-word line controlsignal generators to the sub-word line driver without using a repeater.3. The structure of claim 2, wherein the memory cell array comprises aplurality of memory blocks, each memory block having an area including aplurality of sub-memory blocks arrayed in a first direction, theplurality of memory blocks being arrayed in a second directionintersected to the first direction, and wherein the sub-word line driveris disposed at core regions between the sub-memory blocks.
 4. Thestructure of claim 1, wherein a supply line of the sub-word line controlsignal is disposed overlapping on at least one memory block area in afirst direction, to supply the sub-word line control signal to at leastone sub-word line driver adapted within the one memory block area. 5.The structure of claim 2, wherein the predefined voltage level is a VPPvoltage level higher than an array voltage supplied to the memory cellarray.
 6. The structure of claim 5, wherein the at least two sub-wordline control signal generators generate the sub-word line control signalin response to an address signal.
 7. The structure of claim 3, wherein asupply line is disposed so as to simultaneously supply the sub-word linecontrol signal from the at least two sub-word line control signalgenerators to sub-word line drivers included in at least two memoryblocks.
 8. A semiconductor memory device comprising: a plurality ofmemory blocks, each memory block having an area including a plurality ofsub-memory blocks arrayed in a first direction, the plurality of memoryblocks being arrayed in a second direction that intersects the firstdirection; a plurality of sub-word line control signal generatorsconfigured to supply a sub-word line control signal, wherein at leasttwo of the plurality of sub-word line control signal generatorscorrespond to one sub-word line of a sub-memory block, the at least twogenerators being disposed, respectively, at edge areas of a memory blockand generating an equal sub-word line control signal; a plurality ofsub-word line drivers configured to supply a signal having the samelevel as the sub-word line control signal, the plurality of sub-wordline drivers being disposed in a core region between the sub-memoryblocks; and control signal supply lines for directly supplying thesub-word line control signal to the plurality of sub-word line driverswithout using a repeater, the sub-word line control signal beinggenerated using the sub-word line control signal generators.
 9. Thedevice of claim 8, wherein each of the sub-word line control signalgenerators generates a sub-word line control signal of a predefinedvoltage level in response to an address signal.
 10. The device of claim9, wherein the sub-word line control signal is supplied to at least onesub-word line driver of one memory block selected without being suppliedto other memory blocks.
 11. The device of claim 10, wherein the controlsignal supply lines comprise a first supply line disposed in a firstdirection, and a second supply line disposed in a second directionintersecting the first direction.
 12. The device of claim 11, whereinthe first supply line is coupled between the at least two sub-word linecontrol signal generators that are disposed at both edge areas of thememory block in the first direction, and the second supply line isdisposed to couple at least one corresponding sub-word line driver withthe first supply line.
 13. The device of claim 12, wherein the firstsupply line is disposed overlapping on the memory block area.
 14. Thedevice of claim 13, wherein the at least two sub-word line controlsignal generators generate the sub-word line control signal responsiveto a block selection signal.
 15. The device of claim 9, wherein thepredefined voltage level is a VPP voltage level higher than an operationvoltage of a semiconductor memory array.
 16. The device of claim 9,wherein the sub-word line control signal is configured to be supplied toat least two adjacent memory blocks.
 17. A layout structure of asub-word line control signal generator configured to supply a sub-wordline control signal to a sub-word line driver to enable a sub-word lineof a memory cell array, the structure characterized in that the sub-wordline control signal generator corresponds to one sub-word line driver,the sub-word line control signal generator being divided into a maingenerator and a sub-generator for simultaneously supplying the sub-wordline control signal to at least one supply line, the main generator andthe sub-generator being disposed, respectively, at edge areas of thememory cell array and the main generator and the sub-generatorgenerating an equal sub-word line control signal.
 18. The structure ofclaim 17, wherein the main generator is disposed at a row decoder areaabout an edge area of the memory cell array, and the sub-generator isdisposed at an area opposite to a layout area of the main generator. 19.The structure of claim 18, wherein the memory cell array comprises aplurality of memory blocks arrayed in a second direction intersected toa first direction, each memory block including a plurality of sub-memoryblocks arrayed in the first direction, the sub-word line driver beingdisposed in core regions within an area of each memory block.
 20. Thestructure of claim 17, wherein the at least one supply line is disposedoverlapping the memory block in a first direction.